AUTOMATED TRANSISTOR SIZING METHODOLOGY FOR ANALOG CIRCUITS BASED ON SIMULATED ANNEALING AND COMPACT MODEL OF gm/ID CHARACTERISTICS

This paper presents a transistor sizing methodology for analog CMOS circuits that combines the physics-based gm/ID characteristics provided by the ACM compact model and the simulated annealing technique for the circuit optimization. The methodology exploits different transistor widths and lengths and provides good solutions in a reasonable CPU time, with a single technologydependent curve and accurate expressions for transconductance and current in all operation relgions. The advantage of constraining the optimization within a power budget is of great importance for the designer. As an example, we show the optimization results obtained for the design of a two-stage operational amplifier.